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SPLC780C SP
16COM/40SEG Controller/Driver 16
OCT. 03, 2001 Version 1.0
SUNPLUS TECHNOLOGY CO. reserves the right to change this documentation without prior notice. Information provided by SUNPLUS TECHNOLOGY CO. is believed to be accurate and reliable. However, SUNPLUS TECHNOLOGY CO. makes no warranty for any errors which may appear in this document. No responsibility is assumed by Contact SUNPLUS TECHNOLOGY CO. to obtain the latest version of device specifications before placing your order.
SUNPLUS TECHNOLOGY CO. for any infringement of patent or other rights of third parties which may result from its use. In addition, SUNPLUS products are not authorized for use as critical components in life support devices/ systems or aviation devices/systems, where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Sunplus.
SPLC780C
Table of Contents
PAGE
1. GENERAL DESCRIPTION.......................................................................................................................................................................... 4 2. FEATURES.................................................................................................................................................................................................. 4 3. BLOCK DIAGRAM ...................................................................................................................................................................................... 4 4. SIGNAL DESCRIPTIONS ........................................................................................................................................................................... 5 5. FUNCTIONAL DESCRIPTIONS.................................................................................................................................................................. 6 5.1. OSCILLATOR .......................................................................................................................................................................................... 6 5.2. CONTROL AND DISPLAY INSTRUCTIONS ................................................................................................................................................... 6 5.3. INSTRUCTION TABLE............................................................................................................................................................................... 8 5.4. 8-BIT OPERATION AND 8-DIGIT 1-LINE DISPLAY (USING INTERNAL RESET)................................................................................................ 9 www..com 5.5. 4-BIT OPERATION AND 8-DIGIT 1-LINE DISPLAY (USING INTERNAL RESET).............................................................................................. 10 5.6. 8-BIT OPERATION AND 8-DIGIT 2-LINE DISPLAY (USING INTERNAL RESET).............................................................................................. 10 5.7. RESET FUNCTION .................................................................................................................................................................................11 5.8. DISPLAY DATA RAM (DD RAM) ........................................................................................................................................................... 13 5.9. TIMING GENERATION CIRCUIT............................................................................................................................................................... 13 5.10. LCD DRIVER CIRCUIT ....................................................................................................................................................................... 13 5.11. CHARACTER GENERATOR ROM (CG ROM) ...................................................................................................................................... 13 5.12. CHARACTER GENERATOR RAM (CG RAM) ....................................................................................................................................... 13 5.13. CURSOR/BLINK CONTROL CIRCUIT .................................................................................................................................................... 17 5.14. INTERFACING TO MPU....................................................................................................................................................................... 17 5.15. SUPPLY VOLTAGE FOR LCD DRIVE .................................................................................................................................................... 17 5.16. REGISTER --- IR (INSTRUCTION REGISTER) AND DR (DATA REGISTER) ............................................................................................ 20 5.17. BUSY FLAG (BF) ............................................................................................................................................................................... 20 5.18. ADDRESS COUNTER (AC).................................................................................................................................................................. 20 5.19. I/O PORT CONFIGURATION ................................................................................................................................................................ 20 6. ELECTRICAL SPECIFICATIONS ............................................................................................................................................................. 21 6.1. ABSOLUTE MAXIMUM RATINGS ............................................................................................................................................................. 21 6.2. DC CHARACTERISTICS (VDD = 2.7V TO 4.5V, TA = 25) .................................................................................................................... 21 6.3. AC CHARACTERISTICS (VDD = 2.7V TO 4.5V, TA = 25) .................................................................................................................... 22 6.4. DC CHARACTERISTICS (VDD = 4.5V TO 5.5V, TA = 25) .................................................................................................................... 23 6.5. AC CHARACTERISTICS (VDD = 4.5V TO 5.5V, TA = 25) .................................................................................................................... 23 7. APPLICATION CIRCUITS......................................................................................................................................................................... 26 7.1. R-OSCILLATOR .................................................................................................................................................................................... 26 7.2. INTERFACE TO MPU............................................................................................................................................................................. 26 7.3. SPLC780C APPLICATION CIRCUIT ....................................................................................................................................................... 27 7.4. APPLICATIONS FOR LCD ...................................................................................................................................................................... 28 8. CHARACTER GENERATOR ROM ........................................................................................................................................................... 30 8.1. SPLC780C - 01.................................................................................................................................................................................. 30 8.2. SPLC780C - 02.................................................................................................................................................................................. 31 8.3. SPLC780C - 03.................................................................................................................................................................................. 32 8.4. SPLC780C - 08.................................................................................................................................................................................. 33 8.5. SPLC780C - 11 .................................................................................................................................................................................. 34 8.6. SPLC780C - 12.................................................................................................................................................................................. 35 (c) Sunplus Technology Co., Ltd. Proprietary & Confidential 2 OCT. 03, 2001 Version: 1.0
SPLC780C
8.7. SPLC780C - 13.................................................................................................................................................................................. 36 8.8. SPLC780C - 14.................................................................................................................................................................................. 37 8.9. SPLC780C - 15.................................................................................................................................................................................. 38 8.10. SPLC780C - 17 ............................................................................................................................................................................... 39 8.11. SPLC780C - 18 ............................................................................................................................................................................... 40 8.12. SPLC780C - 19 ............................................................................................................................................................................... 41 9. PACKAGE/PAD LOCATIONS ................................................................................................................................................................... 42 9.1. PAD ASSIGNMENT ............................................................................................................................................................................... 42 9.2. ORDERING INFORMATION ..................................................................................................................................................................... 42 9.3. PAD LOCATIONS .................................................................................................................................................................................. 43 9.4. PACKAGE CONFIGURATION ................................................................................................................................................................... 44
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9.5. PACKAGE INFORMATION ....................................................................................................................................................................... 45
10. DISCLAIMER............................................................................................................................................................................................. 46 11. REVISION HISTORY ................................................................................................................................................................................. 47
(c) Sunplus Technology Co., Ltd. Proprietary & Confidential
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SPLC780C
16COM/40SEG CONTROLLER/DRIVER
1. GENERAL DESCRIPTION
The SPLC780C, a dot-matrix LCD controller and driver from SUNPLUS, is a unique design for displaying alpha-numeric, Japanese-Kana characters and symbols. The SPLC780C A single By provides two types of interfaces to MPU: 4-bit and 8-bit interfaces. The transferring speed of 8-bit is twice faster than 4-bit. SPLC780C is able to display up to two 8-character lines. be extended. rank.
2. FEATURES
! Character generator ROM: 10880 bits Character font 5 x 8 dots: 192 characters Character font 5 x 10 dots: 64 characters ! Character generator RAM: 512 bits Character font 5 x 8 dots: 8 characters Character font 5 x 10 dots: 4 characters ! 4-bit or 8-bit MPU interfaces ! Direct driver for LCD: 16 COMs x 40 SEGs ! Duty factor (selected by program): 1/8 duty: 1 line of 5 x 8 dots 1/11 duty: 1 line of 5 x 10 dots 1/16 duty: 2 lines of 5 x 8 dots / line ! Built-in power on automatic reset circuit ! Built-in oscillator circuit (with external resistor) ! Support external clock operation ! Low Power Consumption ! Package form: 80 QFP or bare chip available
cascading with SPLC100 or SPLC063, the display capability can The CMOS technology ensures the power saves in the most efficient way and the performance keeps in the highest
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3. BLOCK DIAGRAM
OSC1 OSC2 VDD VSS CL1,CL2 M 40-bit Shift Register
40
Timing Generation Circuit Parallel to Serial Data Conversion Circuit Busy Flag 5 Character Generator ROM 8 7 7 8 Instruction Register 8 Instruction Decorder 7 Display Data RAM 80 Bytes 16-bit 16 Shift Register 5 Character Generator RAM 8 Cursor Blink Control Circuit 8
D
DB0-DB3 DB4-DB7 RS R/W E Power Supply for LCD Drive : (V1-V5) I/O Buffer 8 Data Register
Latch Circuit
40
40 Segments x 16 Commons LCD Driver
COM1COM16
7
SEG1SEG40
Address Counter
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SPLC780C
4. SIGNAL DESCRIPTIONS
Mnemonic VDD VSS OSC1 OSC2 V1 - V5 E RW RS PIN No. 33 23 24 25 26 - 30 38 37 36 I I I I Type I I Power input Ground Both OSC1 and OSC2 are connected to resistor for internal oscillator circuit. external clock operation, the clock is input to OSC1. Supply voltage for LCD driving. A start signal for reading or writing data. A signal for selecting read or write actions. 1: Read, 0: Write. A signal for selecting registers. 1: Data Register (for read and write) 0: Instruction Register (for write), Busy flag - Address Counter (for read). DB0 - DB3 DB4 - DB7 CL1 CL2 M D SEG1 - SEG22 SEG23 - SEG40 COM1 - COM16 39 - 42 43 - 46 31 32 34 35 22 - 1 80 - 63 47 - 62 O Common signals for LCD. I/O I/O O O O O O Low 4-bit data High 4-bit data Clock to latch serial data D. Clock to shift serial data D. Switch signal to convert LCD waveform to AC. Sends character pattern data corresponding to each common signal serially. 1: Selection, 0: Non-selection. Segment signals for LCD. For Description
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SPLC780C
5. FUNCTIONAL DESCRIPTIONS
5.1. Oscillator
SPLC780C oscillator supports not only the internal oscillator operation, but also the external clock operation. S=1 S=1 I/D=1 I/D=0 It shifts the display to the left It shifts the display to the right
5.2. Control and Display Instructions
Control and display instructions are described in details as follows:
5.2.4. Display ON/OFF control
RS Code 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 1 D C B
5.2.1. Clear display
RS Code 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 1
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It clears the entire display and sets Display Data RAM Address 0 in Address Counter.
D = 1: Display on, D = 0: Display off C = 1: Cursor on, C = 0: Cursor off B = 1: Blinks on, B= 0: Blinks off
5.2.2. Return home
RS Code 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 1 X
5 x 8 dot character font
5 x 10 dot character font
8th line
X: Do not care (0 or 1) It sets Display Data RAM Address 0 in Address Counter and the display returns to its original position. displayed). change. The cursor or blink goes to the most-left side of the display (to the 1st line if 2 lines are The contents of the Display Data RAM do not
Cursor
11th line
5.2.5. Cursor or display shift
Without changing DD RAM data, it moves cursor and shifts display.
RS Code 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 S/C R/L X X
5.2.3. Entry mode set
During writing and reading data, it defines cursor moving direction and shifts the display.
RS Code 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 1 I/D S
Blink display alternately
I / D = 1: Increment, I / D = 0: Decrement. S = 1: The display shift, S = 0: The display does not shift.
S/C 0 0 1 1
R/L 0 1 0 1 Shift cursor to the left Shift cursor to the right Shift display to the left. Shift display to the right.
Description
Address Counter AC = AC - 1 AC = AC + 1
Cursor follows the display shift Cursor follows the display shift
AC = AC AC = AC
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5.2.6. Function set
Display data RAM can be read or written after this setting.
RS Code 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 1 DL N F X X
In one-line display (N = 0), (aaaaaaa)2: (00)16 - (4F)16.
X: Do not care (0 or 1) DL: It sets interface data length. DL = 1: Data transferred with 8-bit length (DB7 - 0). DL = 0: Data transferred with 4-bit length (DB7 - 4). It requires two times to accomplish data transferring. N: It sets the number of the display line. N = 0: One-line display.
In two-line display (N = 1), (aaaaaaa)2: (00)16 - (27)16 for the first line, (aaaaaaa)2: (40)16 - (67)16 for the second line.
5.2.9. Read busy flag and address
RS Code 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 BF a a a a a a a
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F: It sets the character font. F = 0: 5 x 8 dots character font. F = 1: 5 x 10 dots character font.
When BF = 1, it indicates the system is busy now and it will not accept any instruction until not busy (BF = 0). At the same time, Character Font Duty Factor 5 x 8 dots 5 x 10 dots 5 x 8 dots 1/8 1 / 11 1 / 16 the content of Address Counter (aaaaaaa)2 is read.
N 0 0 1
F 0 1 X
No. of Display Lines 1 1 2
5.2.10. Write data to character generator RAM or display data RAM
RS Code 1 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 d d d d d d d d
It cannot display two lines with 5 x 10 dots character font.
5.2.7. Set character generator RAM address
RS Code 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 a a a a a a
It writes data (dddddddd)2 to character generator RAM or display data RAM.
5.2.11. Read data from character generator RAM or
It sets Character Generator RAM Address (aaaaaa)2 to the Address Counter.
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 d d d d d d d d
display data RAM
Character Generator RAM data can be read or written after this setting.
Code
1
5.2.8. Set display data RAM address
RS Code 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 1 a a a a a a a
It reads data (dddddddd)2 from character generator RAM or display data RAM. To read data correctly, do the following: 1). The address of the Character Generator RAM or Display Data RAM or shift the cursor instruction.
It sets Display Data RAM Address (aaaaaaa)2 to the Address Counter.
2). The " Read " instruction.
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SPLC780C
5.3. Instruction Table
Instruction Clear Display Return Home Instruction Code RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 Description Write "20H" to DDRAM and set DDRAM address to "00H" from AC Set DDRAM address to "00H" from AC and return cursor to its original position if shifted. changed. Entry Mode Set Display ON/ 0 0 0 0 0 0 0 0 0 0 0 1 1 D C B 0 0 0 0 0 0 0 1 I/D S Assign cursor moving direction and enable the shift of entire display Set display(D), cursor(C), and blinking of cursor(B) on/off control bit. S/C R/L Set cursor moving and display shift control bit, and the direction, without changing of DDRAM data. Function Set 0 0 0 0 1 DL N F Set interface data length (DL: 8-bit/4-bit), numbers of display line (N: 2-line/1-line) and, display font type (F:5x10 dots/5x8 dots) Set CGRAM Address Set DDRAM Address Read Busy Flag and Address Counter Write Data to RAM Read Data from RAM
Note: "-": don't care
Execution time (fosc=270KHz) 1.52ms 1.52ms
The contents of DDRAM are not 38s 38s 38s
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Cursor or Display Shift
38s
0 0 0
0 0 1
0 1
1
AC5 AC4 AC3 AC2 AC1 AC0 Set CGRAM address in address counter.
38s 38s
AC6 AC5 AC4 AC3 AC2 AC1 AC0 Set DDRAM address in counter
BF AC6 AC5 AC4 AC3 AC2 AC1 AC0 Whether during internal operation or not can be known by reading BF. read. The contents of address counter can also be
1 1
0 1
D7 D7
D6 D6
D5 D5
D4 D4
D3 D3
D2 D2
D1 D1
D0 Write D0 Read
data data
into from
internal internal
RAM RAM
38s 38s
(DDRAM/CGRAM). (DDRAM/CGRAM).
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SPLC780C
5.4. 8-Bit Operation and 8-Digit 1-Line Display (Using Internal Reset)
No. 1 2 Instruction Power on. (SPLC780C starts initializing) Function set
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Display Power on reset. No display.
Operation
Set to 8-bit operation and select 1-line display line and character font.
0
0
0
0
1
1
0
0
X
X
3
Display on / off control
0 0 0 0 0 0 1 1 1 0
_
Display on. Cursor appear. Increase address by one.
4
Entry mode set
0 0 0 0 0 0 0 1 1 0
_
It will shift the cursor to the right when writing to the DD RAM/CG RAM. Now the display has no shift.
5
Write data to CG RAM / DD RAM
0
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6
1 0 0 1
1
0
1
1
1
W_
Write " W ". The cursor is incremented by one and shifted to the right. Write " E ". The cursor is incremented by one and shifted to the right. :
Write data to CG RAM / DD RAM
0 0 0 1 0 1
WE_
7 8
: Write data to CG RAM / DD RAM
1 0 0 1 0 0 0 1 0 1
WELCOME_
Write " E ". The cursor is incremented by one and shifted to the right. Set mode for display shift when writing
9
Entry mode set
0 0 0 0 0 0 0 1 1 1
WELCOME_
10
Write data to CG RAM / DD RAM
1 0 0 0 1 0 0 0 0 0
ELCOME _
Write "
"(space).
The cursor is incremented by one and shifted to the right. Write " C ". The cursor is incremented by one and shifted to the right.
11
Write data to CG RAM / DD RAM
1 0 0 1 0 0 0 0 1 1
LCOME C_
12 13
1 0 0 1 0
: Write data to CG RAM / DD RAM
1 1 0 0 1
:
COMPAMY_
Write " Y ". The cursor is incremented by one and shifted to the right.
14
Cursor or display shift
0 0 0 0 0 1 0 0 X X
COMPAMY_
Only shift the cursor's position to the left (Y).
15
Cursor or display shift
0 0 0 0 0 1 0 0 X X
COMPAMY_
Only shift the cursor's position to the left (M).
16
Write data to CG RAM / DD RAM
1 0 0 1 0 0 1 1 1 0
OMPANY_
Write " N ". The display moves to the left.
17
Cursor or display shift
0 0 0 0 0 1 1 1 X X
COMPAMY_
Shift the display and the cursor's position to the right.
18
Cursor or display shift
0 0 0 0 0 1 0 1 X X
OMPANY_
Shift the display and the cursor's position to the right.
19
Write data to CG RAM / DD RAM
1 0 0 1 0 0 0 0 0 0
COMPAMY_
Write "
" (space).
The cursor is incremented by one and shifted to the right. :
20 21 Return home
0 0 0 0 0
:
0 0 0 1 0
:
WELCOME_
Both the display and the cursor return to the original position (address 0).
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SPLC780C
5.5. 4-Bit Operation and 8-Digit 1-Line Display (Using Internal Reset)
No. 1 Power on. (SPLC780C starts initializing) Instruction Display Operation
Power on reset. No display.
2
Function set
RS R/W DB7 DB6 DB5 DB4 0 0
0 0
Set to 4-bit operation.
0
0 0
0
0 0
1
1 X
0
0 X
3
0 0
Set to 4-bit operation and select 1-line display line and character font.
4
0 0
0 0
0 1
0 1
0 1
0
_
0
Display on. Cursor appears.
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0 0 0
0 1
0 1
0 0
Increase address by one.
_
It will shift the cursor to the right when writing to the DD RAM / CG RAM. Now the display has no shift.
6
1 1
0 0
0 0
1 1
0 1
1
W_
1
Write " W ". The cursor is incremented by one and shifted to the right.
5.6. 8-Bit Operation and 8-Digit 2-Line Display (Using Internal Reset)
No. 1 2 Power on. (SPLC780C starts initializing) Function set
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 1 1 0 X X
Instruction
Display Power on reset. No display.
Operation
Set to 8-bit operation and select 2-line display line and 5 x 8 dot character font.
Display on. Cursor appear. Increase address by one.
0 0 0 1 1 0
3
Display on / off control
0
0
_
0
1
1
1
0
0
0
0
4
Entry mode set
0 0 0 0
_
It will shift the cursor to the right when writing to the DD RAM / CG RAM. Now the display has no shift.
5
Write data to CG RAM / DD RAM
1 0 0 1 0 1 0 1 1 1
W_
Write " W ". The cursor is incremented by one and shifted to the right. : : Write " E ". The cursor is incremented by one and shifted to the right.
6 7
: Write data to CG RAM / DD RAM
1 0 0 1 0 0 0 1 0 1
WELCOME_
8
Set DD RAM address
0 0 1 1 0 0 0 0 0 0
WELCOME _
It sets DD RAM's address. The cursor is moved to the beginning position of the 2nd line. Write " T ". The cursor is incremented by one and shifted to the right. :
9
Write data to CG RAM / DD RAM
1 0 0 1 0 1 0 1 0 0
WELCOME T_
10 11
: Write data to CG RAM / DD RAM
1
:
WELCOME TO PART_
Write " T ". The cursor is incremented by one and shifted to the right.
0
0
1
0
1
0
1
0
0
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SPLC780C
No. 12 Entry mode set
0 0 0 0 0 0 0 1 1 1
Instruction
Display
WELCOME TO PART_
Operation When writing, it sets mode for the display shift.
13
Write data to CG RAM / DD RAM
1 0 0 1 0 1 1 0 0 1
ELCOME O PARTY_
Write " Y ". The cursor is incremented by one and shifted to the right. : Both the display and the cursor return to the original position (address 0).
14 15 Return home
0 0 0 0 0
:
:
WELCOME TO PARTY
0
0
0
1
0
5.7. Reset Function
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follows:
At power on, SPLC780C starts the internal auto-reset circuit and executes the initial instructions.
The initial procedures are shown as
[ 8-Bit Interface ]
Power On
W ait time > 15 ms after VDD > 4.5V
W ait time > 40ms After VDD > 2.7V
RS R/W DB7 DB6 DB5 DB4 DB3 DB3 DB1 DB0 00 0 0 1 1 X X X X
BF cannot be checked before this instruction . Function set ( Interface is 8 bits length . )
W ait time > 4.1 ms
RS R/W DB7 DB6 DB5 DB4 DB3 DB3 DB1 DB0 00 0 0 1 1 X X X X
BF cannot be checked before this instruction . Function set ( Interface is 8 bits length . )
W ait time > 100 us
RS R/W DB7 DB6 DB5 DB4 DB3 DB3 DB1 DB0 00 0 0 1 1 X X X X
BF cannot be checked before this instruction . Function set ( Interface is 8 bits length . )
BF can be checked after the following instructions . Function set ( Interface is 8 bits length . Specify the number of display lines and character font . ) The number of display lines and character font cannot be changed afterwards . Display off Display clear
Initialization Ends
RS R/W DB7 DB6 DB5 DB4 DB3 DB3 DB1 DB0 0 0 0 0 1 1 N F X X
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
I/D
S
Entry mode set
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SPLC780C
[ 4-Bit Interface ]
Power On
W ait time > 15 ms after VDD > 4.5V
W ait time > 40ms After VDD > 2.7V
RS R/W DB7 DB6 DB5 DB4 0 0 0 0 1 1
BF cannot be checked before this instruction . Function set ( Interface is 8 bits length . )
W ait time > 4.1 ms
RS www..com R/W 0 0
DB7 DB6 DB5 DB4 0 0 1 1
BF cannot be checked before this instruction . Function set ( Interface is 8 bits length . )
W ait time > 100 us
RS R/W DB7 DB6 DB5 DB4 0 0 0 0 1 1
BF cannot be checked before this instruction . Function set ( Interface is 8 bits length . )
RS R/W DB7 DB6 DB5 DB4 0 0 0 0 1 0 0 0
0 0
0 0
0 0
BF can be checked after the following instructions . Function set ( Set interface to be 4 bits length) Interface is 8 bits length .
Function set ( Interface is 4 bits length . Specify the number of the display lines and character font . )
0 0
0 0
0 0
0 0
0 N
0 1
0 0
0 0
0 F
0 0
0 0
0 1
1 X
0 0
0 0
0 I/D
0 X
0 0
0 1
0 S
The number of display lines and character font cannot be changed afterwards . Display off Display clear
Initialization Ends
Entry mode set
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SPLC780C
5.8. Display Data RAM (DD RAM)
The 80-bit DD RAM is normally used for storing display data. Those DD RAM not used for display data can be used as general data RAM. Its address is configured in the Address Counter. The relationships between Display Data RAM Address and LCDs position are depicted as follows.
1-line display , 80 display characters 1 2 3 4 5 6 00 01 02 03 04 05
79 4E
80 4F
Display position Display data RAM address
( Example ) 1-line display , 8 display characters 1 2 3 4 5 6 7 8
Display position Display data RAM address
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02
03
04
05
06
07
When the display shift operation is performed , the display data RAM's address moves as : ( i ) Left shift 01 02 03 04 05 06 06 07 08 ( ii ) Right shift 4F 00 01 02 03 04 05 06
5.9. Timing Generation Circuit
The timing generating circuit is able to generate timing signals to the internal circuits. In order to prevent the internal timing interface, the MPU access timing and the RAM access timing are generated independently.
5.11. Character Generator ROM (CG ROM)
Using 8-bit character code, the character generator ROM generates 5 x 8 dots or 5 x 10 dots character patterns. dots character patterns. It also can generate 192's 5 x 8 dots character patterns and 64's 5 x 10
5.10. LCD Driver Circuit
Total of 16 commons and 40 segments signal drivers are valid in the LCD driver circuit. When a program specifies the character fonts and line numbers, the corresponding common signals output drive-waveforms and the others still output unselected waveforms.
5.12. Character Generator RAM (CG RAM)
Users can easily change the character patterns in the character generator RAM through program. It can be written to 5 x 8 dots, 8-character patterns or 5 x 10 dots for 4-character patterns.
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SPLC780C
The following diagram shows the SPLC780C character patterns: Correspondence between Character Codes and Character Patterns.
Higher 4-bit (D4 to D7) of Character Code (Hexadecimal) 0 CG RAM (1) 1 2 3 4 5 6 7 8 9 A B C D E F
0
1
CG RAM (2) CG RAM (3)
2
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3
CG RAM (4) CG RAM (5) CG RAM (6) CG RAM (7) CG RAM (8) CG RAM (1) CG RAM (2) CG RAM (3) CG RAM (4) CG RAM (5) CG RAM (6) CG RAM (7) CG RAM (8)
4
5 Lower 4-bit (D0 to D3) of Character Code (Hexadecimal)
6
7
8
9
A
B
C
D
E
F
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SPLC780C
The relationships between Character Generator RAM Addresses, Character Generator RAM Data (character patterns), and Character Codes are depicted as follows:
5.12.1. 5 x 8 dot character patterns
Character Code ( DD RAM Data ) b7 b6 b5 b4 b3 b2 b1 b0
CG RAM Address b5 b4 b3 b2 b1 b0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 X X
Character Patterns ( CG RAM Data ) b7 b6 b5 b4 b3 b2 b1 b0 1 0 0 X X 0 0 0 0 0 0 0 0 X X 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Character Pattern Example (2) Cursor Position Character Pattern Example (1)
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0
X
0
0
0
0
0
0
0
0
0
0
X
0
0
1
0
0
1
Note1:
It means that the bit0~2 of the character code correspond to the bit3~5 of the CG RAM address.
Note2:
These areas are not used for display, but can be used for the general data RAM.
Note3: When all of the bit4-7 of the character code are 0, CG RAM character patterns are selected. Note4: " 1 ": Selected, " 0 " : No selected , " X " : Do not care (0 or 1). Note5: For example (1), set character code (b2 = b1 = b0 = 0, b3 = 0 or 1, b7-b4 = 0) to display " T ". display " T " character. Note6: The bits 0-2 of the character code RAM is the character pattern line position. with the cursor. The 8th line is the cursor position and display is formed by logical OR That means character code (00) 16,and (08) 16 can
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5.12.2. 5 X 10 dot character patterns
Character Code ( DD RAM Data ) b7 b6 b5 b4 b3 b2 b1 b0
CG RAM Address b5 b4 b3 b2 b1 b0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 X X
Character Patterns ( CG RAM Data ) b7 b6 b5 b4 b3 b2 b1 b0 1 1 1 1 1 X X 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 1 1 1 0 Cursor Position Character Pattern Example (1)
0
0
0
0
X
0
0
X
0
0
0 0 0 1 1 1 1 1 1 1 1
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X
X
X
X
X
X
X
Note1:
It means that the bit1~2 of the character code correspond to the bit4~5 of the CG RAM address.
Note2:
These areas are not used for display, but can be used for the general data RAM.
Note3: When all of the bit4-7 of the character code are 0, CG RAM character patterns are selected. Note4: " 1 ": Selected, " 0 ": No selected, " X ": Do not care (0 or 1). Note5: For example (1), set character code (b2 = b1 = 0, b3 = b0 = 0 or 1, b7-b4 = 0) to display " U ". (08) 16,and (09) 16 can display " U " character. Note6: The bits 0-3 of the character code RAM is the character pattern line position. with the cursor. The 11th line is the cursor position and display is formed by logical OR That means all of the character codes (00) 16, (01) 16,
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5.13. Cursor/Blink Control Circuit
This circuit generates the cursor or blink in the cursor / blink control circuit. The cursor or the blink appears in the digit at the Display Data RAM Address defined in the Address Counter. When the Address Counter is (07) 16, the cursor position is shown as belows:
b6 AC 0
b5 0
b4 0
b3 0
b2 1
b1 1
b0 1
In a 1-line display digit 1 00 2 01 3 02 4 03 5 04 6 05 7 06 8 07 9 08 10 09 Display position Display data RAM address ( Hexadecimal ) the cursor position In a 2-line display digit 1st line 2nd line 1 00 40 2 01 41 3 02 42 4 03 43 5 04 44 6 05 45 7 06 46 8 07 47 9 08 48 10 09 49 Display position Display data RAM address ( Hexadecimal )
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the cursor position
5.14. Interfacing to MPU
There are two types of data operations: 4-bit and 8-bit operations. Using 4-bit MPU, the interfacing 4-bit data is transferred by 4-busline (DB4 to DB7). used. transferring. Thus, DB0 to DB3 bus lines are not Using 4-bit MPU to interface 8-bit data requires two times First, the higher 4-bit data is transferred by Secondly, the lower
5.15. Supply Voltage for LCD Drive
Different voltages can be supplied to SPLC780C's pins (V5 - 1) for obtaining LCD drive-waveform. The relationships between bias, duty factor and supply voltages are shown as belows:
Duty Factor Supply Voltage V1 V2 V3 V4 V5
1/8, 1/11 1/4 VDD - 1/4 VLCD VDD - 1/2 VLCD VDD - 1/2 VLCD VDD - 3/4 VLCD VDD - VLCD
1/16 1/5 VDD - 1/5 VLCD VDD - 2/5 VLCD VDD - 3/5 VLCD VDD - 4/5 VLCD VDD - VLCD
4-busline (for 8-bit operation, DB7 to DB4). DB0).
4-bit data is transferred by 4-busline (for 8-bit operation, DB3 to For 8-bit MPU, the 8-bit data is transferred by 8-buslines (DB0 to DB7).
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5.15.1. The power connections for LCD (1/4 Bias, 1/5 Bias) are shown belows:
VDD ( +5.0V ) VDD R V1 V2 V3 V4 R V5 VR 1 / 4 Bias (1/8,1/11 Duty) -V or Gnd 1 / 5 Bias (1/16 Duty) -V or Gnd V5 VR R VLCD R V3 V4 R R V1 V2 R VLCD VDD ( +5.0V )
VDD R
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The bypass-capacitor improves the LCD display quality.
VDD( +5.0V ) VDD R V1 R C C V1 VDD
VDD( +5.0V )
R
C
R V2 R
C
V2 V3
R C
V3 R V4
C
V4 R V5 VR 1 / 4 Bias (1/8,1/11 Duty) -V or Gnd 1 / 5 Bias C
C
R V5
C VR
(1/16 Duty)
-V or Gnd
The bias voltage must have the following relations: VDD > V1 > V2 V3 > V4 > V5.
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5.15.2. The relationship between LCD frames frequency and oscillators frequency.
(Assume the oscillation frequency is 250KHz, 1 clock cycle time = 4.0s)
5.15.2.1. 1/8 Duty, TYPE-B waveform
400 clocks 12 VPP V1 COM1 V2(V3) V4 VSS 1 Frame 1 Frame 7812 7812 7812 78
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1 frame = 4(s) x 400 x 8 = 12800(s) = 12.8ms 1 Frame frequency = = 78.1(Hz) 12.8(ms)
5.15.2.2. 1/11 Duty, TYPE-B waveform
400 clocks 12 VPP V1 COM1 V2(V3) V4 VSS 1 Frame 1 frame = 4(s) x 400 x 11 = 17600(s) = 17.6ms Frame frequency = 1 17.6(ms) = 5 6 .8(Hz) 1 Frame 10 11 1 2 10 11 1 2
5.15.2.3. 1/16 Duty, TYPE-B waveform
200 clocks 12 VPP V1 COM1 V2 V3 V4 VSS 1 Frame 1 frame = 4(s) x 200 x 16 = 12800(s) = 12.8ms 1 Frame frequency = = 78.1(Hz) 12.8(ms) 1 Frame 15 16 1 2 15 16 1 2
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5.16. REGISTER --- IR (Instruction Register) and DR (Data Register)
SPLC780C contains two 8-bit registers: Instruction Register (IR) and Data Register (DR). Using combinations of the RS pin and the R/W pin selects the IR and DR, see below:
5.19. I/O Port Configuration 5.19.1. Input port: E
VDD PMOS
RS
R/W
Operation
0 0 1
0 1 0
IR write (Display clear, etc.) Read busy flag (DB7) and Address Counter (DB0 - DB6) DR write (DR to Display data RAM or Character generator RAM)
NMOS
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5.19.2. Input port: R / W, RS
VDD PMOS VDD PMOS
read (Display data RAM or Character
generator RAM to DR)
The IR can be written by MPU, but it cannot be read by MPU.
5.17. Busy Flag (BF)
When RS = 0 and R/W = 1, the busy flag is output to DB7. As the busy flag =1, SPLC780C is in busy state and does not accept any instruction until the busy flag = 0.
NMOS
5.19.3. Output port: CL1, CL2, M, D 5.18. Address Counter (AC)
The Address Counter assigns addresses to Display Data RAM and Character Generator RAM. When an instruction for address is written in IR, the address information is sent from IR to AC. After writing to/reading from Display Data RAM or Character Generator RAM, AC is automatically incremented by one (or decremented by one). The contents of AC are output to DB0 DB6 when RS = 0 and R/W = 1.
NMOS VDD PMOS
5.19.4. Input / Output port: DB7 - 0
VDD VDD
VDD
Enable
PMOS
PMOS
NMOS
Data
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6. ELECTRICAL SPECIFICATIONS
6.1. Absolute Maximum Ratings
Characteristics Symbol Ratings
Operating Voltage Driver Supply Voltage Input Voltage Range Operating Temperature Storage Temperature
conditions see AC/DC Electrical Characteristics.
VDD VLCD VIN TA TSTO
-0.3V to +7.0V VDD - 12V to VDD + 0.3V -0.3V to VDD + 0.3V -30 to +80 -55 to +125
Note: Stresses beyond those given in the Absolute Maximum Rating table may cause operational errors or damage to the device. For normal operational
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6.2. DC Characteristics (VDD = 2.7V to 4.5V, TA = 25)
Characteristics Symbol Limit Min. Typ. Max. Unit Test Condition
Operating Current Input High Voltage Input Low Voltage Input High Voltage Input Low Voltage Input High Current Input Low Current Output High Voltage (TTL) Output Low Voltage (TTL) Output High Voltage (CMOS) Output Low Voltage (CMOS) Driver ON Resistance (COM) Driver ON Resistance (SEG) LCD Voltage
IDD VIH1 VIL1 VIH2 VIL2 IIH IIL VOH1 VOL1 VOH2 VOL2 RCOM RSEG VLCD
0.7VDD -0.3 0.7VDD -0.2 -1.0 -5.0 0.75VDD 0.8VDD 3.0
0.2 -15 -
0.4 VDD 0.55 VDD 0.2VDD 1.0 -30 0.2VDD 0.2VDD 20 30 11
mA V V V V
External clock (Note) Pins:(E, RS, R/W, DB0 - DB7)
Pin OSC1 Pins: (RS, R/W, DB0 - DB7) VDD = 3.0V IOH = - 0.1mA Pins: DB0 - DB7 IOL = 0.1mA Pins: DB0 - DB7 IOH = - 40A, Pins: CL1, CL2, M, D IOL = 40A, Pins: CL1, CL2, M, D IO = 50A, VLCD = 4.0V Pins: COM1 - COM16 IO = 50A, VLCD = 4.0V Pins: SEG1 - SEG40 VDD-V5, 1/4 bias or 1/5 bias
A A
V V V V K K V
Note: FOSC = 250KHz, VDD = 3.0V, pin E = "L", RS, R/W, DB0 - DB7 are open, all outputs are no loads.
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6.3. AC Characteristics (VDD = 2.7V to 4.5V, TA = 25) 6.3.1. Internal clock operation
Characteristics Symbol Limit Min. Typ. Max. Unit Test Condition
OSC Frequency
FOSC1
190
270
350
KHz
VDD = 3.0V, Rf = 75K2%
6.3.2. External clock operation
Characteristics Symbol Limit Min. Typ. Max. Unit Test Condition
External Frequency
FOSC2
125 45
250 50 -
350 55 0.2
KHz %
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Duty Cycle
Rise/Fall Time
t r, t f
-
s
6.3.3. Write mode (Writing data from MPU to SPLC780C)
Characteristics Symbol Limit Min. Typ. Max. Unit Test Condition
E Cycle Time E Pulse Width E Rise/Fall Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time
tC tPW tR, tF tSP1 tHD1 tSP2 tHD2
1000 450 60 20 195 10
-
25 -
ns ns ns ns ns ns ns
Pin E Pin E Pin E Pins: RS, R/W, E Pins: RS, R/W, E Pins: DB0 - DB7 Pins: DB0 - DB7
6.3.4. Read mode (Reading data from SPLC780C to MPU)
Characteristics Symbol Limit Min. Typ. Max. Unit Test Condition
E Cycle Time E Pulse Width E Rise/Fall Time Address Setup Time Address Hold Time Data Output Delay Time Data hold time
tC tW tR, tF tSP1 tHD1 tD tHD2
1000 450 60 20 5.0
-
25 360 -
ns ns ns ns ns ns ns
Pin E Pin E Pin E Pins: RS, R/W, E Pins: RS, R/W, E Pins: DB0 - DB7 Pin DB0 - DB7
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6.4. DC Characteristics (VDD = 4.5V to 5.5V, TA = 25)
Characteristics Symbol Limit Min. Typ. Max. Unit Test Condition
Operating Current Input High Voltage Input Low Voltage Input High Voltage Input Low Voltage Input High Current Input Low Current Output High www..com Voltage (TTL) Output Low Voltage (TTL) Output High Voltage (CMOS) Output Low Voltage (CMOS) Driver ON Resistance (COM) Driver ON Resistance (SEG) LCD Voltage
IDD VIH1 VIL1 VIH2 VIL2 IIH IIL VOH1 VOL1 VOH2 VOL2 RCOM RSEG VLCD
2.2 -0.3 VDD-1 -0.2 -2.0 -20 2.4 0.9VDD 3.0
0.55 -50 -
0.8 VDD 0.6 VDD 1.0 2.0 -100 VDD 0.4 VDD 0.1VDD 20 30 11
mA V V V V
External clock (Note) Pins:(E, RS, R/W, DB0 - DB7)
Pin OSC1 Pin OSC1 Pins: (RS, R/W, DB0 - DB7) VDD = 5.0V
A A
V V V V K K V
IOH = - 0.1mA Pins: DB0 - DB7 IOL = 0.1mA Pins: DB0 - DB7 IOH = - 40A, Pins: CL1, CL2, M, D IOL = 40A, Pins: CL1, CL2, M, D IO = 50A, VLCD = 4.0V Pins: COM1 - COM16 IO = 50A, VLCD = 4.0V Pins: SEG1 - SEG40 VDD-V5, 1/4 bias or 1/5 bias
Note: FOSC = 250KHz, VDD = 5.0V, pin E = "L", RS, R/W, DB0 - DB7 are open, all outputs are no loads.
6.5. AC Characteristics (VDD = 4.5V to 5.5V, TA = 25) 6.5.1. Internal clock operation
Characteristics Symbol Limit Min. Typ. Max. Unit Test Condition
OSC Frequency
FOSC1
190
270
350
KHz
VDD = 5.0V, Rf = 91K2%
6.5.2. External clock operation
Characteristics Symbol Limit Min. Typ. Max. Unit Test Condition
External Frequency Duty Cycle Rise/Fall Time
FOSC2
125 45
250 50 -
350 55 0.2
KHz %
t r, t f
-
s
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6.5.3. Write mode (Writing Data from MPU to SPLC780C)
Characteristics Symbol Limit Min. Typ. Max. Unit Test Condition
E Cycle Time E Pulse Width E Rise/Fall Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time
tC tPW tR, tF tSP1 tHD1 tSP2 tHD2
500 230 40 10 80 10
-
20 -
ns ns ns ns ns ns ns
Pin E Pin E Pin E Pins: RS, R/W, E Pins: RS, R/W, E Pins: DB0 - DB7 Pins: DB0 - DB7
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Characteristics Symbol Limit Min. Typ. Max. Unit Test Condition
E Cycle Time E Pulse Width E Rise/Fall Time Address Setup Time Address Hold Time Data Output Delay Time Data hold time
tC tW tR, tF tSP1 tHD1 tD tHD2
500 230 40 10 5.0
-
20 120 -
ns ns ns ns ns ns ns
Pin E Pin E Pin E Pins: RS, R/W, E Pins: RS, R/W, E Pins: DB0 - DB7 Pin DB0 - DB7
6.5.5. Interface mode with LCD Driver (SPLC100A1)
Characteristics Symbol Limit Min. Typ. Max. Unit Test Condition
Clock pulse width high Clock pulse width low Clock setup time Data setup time Data hold time M delay time
tPWH tPWL tCSP tDSP tHD tD
800 800 500 300 300 -1000
-
1000
ns ns ns ns ns ns
Pins: CL1, CL2 Pins: CL1, CL2 Pins: CL1, CL2 Pins: D Pins: D Pins: M
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6.5.6. Write mode timing diagram (Writing Data from MPU to SPLC780C)
RS
VIH1 VIL1 tSP1 VIL1
tPW
VIH1 VIL1
tHD1
R/W
VIL1 VIH1 VIL1
tR
E
VIH1 VIL1 tSP2
tF tHD1
VIL1
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DB7 - 0
VIH1 VIL1
tHD2
Valid Data tC
VIH1 VIL1
6.5.7. Read mode timing diagram (Reading Data from SPLC780C to MPU)
RS
VIH1 VIL1 tSP1
VIH1
VIH1 VIL1
tHD1
VIH1
R/W
tPW
E
VIH1 VIL1
tR
tD VIH1 VIL1
VIH1 VIL1
tF tHD1
VIL1
tHD2
DB0 - DB7
Valid Data tC
VIH1 VIL1
6.5.8. Interface mode with SPLC100A1 timing diagram
CL1
0.9VDD
tPWH tCSP
0.9VDD
tPWH
CL2
0.9VDD 0.1VDD 0.1VDD
tCSP
D
0.9VDD 0.1VDD
tPWL
0.9VDD 0.1VDD
tDSP
M
0.1VDD
tHD
tD
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7. APPLICATION CIRCUITS
7.1. R-Oscillator
The oscillation resistor Rf is used only for the internal oscillaotr operation mode.
OSC1 Rf : 75.0K2% ( when VDD = 3.0V) Rf : 91K 2% ( when VDD = 5.0V) Since the oscillation frequency varies depending on the OSC1 and OSC2 pin capacitance, the wiring length to these pins should be minimized.
OSC2
400 Fosc ( KHz )
600
Fosc ( KHz )
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270 200
400 270 200
0 0
75 100
200 Rosc ( Kohms )
300
400
0 0
91 100
200 Rosc ( Kohms )
300
400
VDD = 3.0V
VDD = 5.0V
7.2. Interface to MPU 7.2.1. Interface to 8-bit MPU (6805)
PA0 | PA7
8
DB0 | DB7
COM1 | COM16
16
LCD PANEL 16 COMMONS X
6805
PB0 PB1 PB2
SPLC780C E RS R/W
SEG1 | SEG40
40
40 SEGMENTS
7.2.2. Interface to 8-bit MPU (Z80)
D0 | D7
Z80 A1 | A7 A0
IO RQ
WR
DB0 | DB7
8
7
CO M1 | CO M16
16
LCD PANEL 16 CO MMONS X
E RS
SPLC780C
SEG 1 | SEG40
40
40 SEG MENTS
R/W
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7.3. SPLC780C Application Circuit
DOT MATRIX LCD PANEL 16 (8)
COM16 (COM8) | COM1
40
SEG40 | SEG1
40 Y1-Y40 DL1 VDD FCS SHL1 SHL2 GND VEE
SPLC100A1
DR2 DL2 DR1 CL1 CL2 M
40
SPLC100A1
40
SPLC100A1
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Y1-Y40 DL1 DR2 VDD DL2 FCS DR1 SHL1 CL1 SHL2 CL2 GND M VEE V1V2 V3 V4V5 V6
Y1-Y40 DL1 DR2 VDD DL2 FCS DR1 SHL1 CL1 SHL2 CL2 GND M VEE V1V2 V3 V4V5 V6
V1V2V3 V4V5V6 VDD GND CL1 CL2 M V1 V2 V3 V4 V5 SPLC780C R VDD ( +5V ) C R C R C R
R C C
VR -V or Gnd
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7.4. Applications for LCD
SPLC780C COM1 LCD Panel COM8 SEG1 8 characters x 1 line
SEG40 ( Example 1 ) : 5 x 8 dots , 8 characters x 1 line [ 1 / 4 Bias , 1 / 8 Duty ]
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SPLC780C COM1 LCD Panel 8 characters x 1 line COM11 SEG1
SEG40 ( Example 2 ) : 5 x 10 dots , 8 characters x 1 line [ 1 / 4 Bias , 1 / 11 Duty ]
SPLC780C COM1 LCD Panel COM8 COM9 COM16 SEG1 8 characters x 2 lines
SEG40 ( Example 3 ) : 5 x 8 dots , 8 characters x 2 lines [ 1 / 5 Bias , 1 / 16 Duty ]
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SPLC780C COM1 COM8 SEG1 SEG40 COM9 COM16
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( Example 4 ) : 5 x 8 dots , 16 characters x 1 line [ 1 / 5 Bias , 1 / 16 Duty ]
SPLC780C
SEG1 SEG20 COM1 LCD Panel COM8 4 characters x 2 lines
SEG21 SEG40 ( Example 5 ) : 5 x 8 dots , 4 characters x 2 lines [ 1 / 4 Bias , 1 / 8 Duty ]
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8. CHARACTER GENERATOR ROM
8.1. SPLC780C - 01
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8.2. SPLC780C - 02
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8.3. SPLC780C - 03
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8.4. SPLC780C - 08
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8.5. SPLC780C - 11
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8.6. SPLC780C - 12
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8.7. SPLC780C - 13
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8.8. SPLC780C - 14
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8.9. SPLC780C - 15
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8.10. SPLC780C - 17
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8.11. SPLC780C - 18
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8.12. SPLC780C - 19
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9. PACKAGE/PAD LOCATIONS
9.1. PAD Assignment
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Chip Size: 3140m x 2690m PAD Size: 94m x 94m This IC substrate should be connected to VDD
Note1: Chip size included scribe line. Note2: The 0.1F capacitor between VDD and VSS should be placed to IC as close as possible.
9.2. Ordering Information
Product Number Package Type
SPLC780C-nnnnV-C SPLC780C-nnnnV-P
Note1: Code number (nnnnV) is assigned for customer. Note2: Code number (nnnn = 0000 - 9999); version (V = A - Z).
Chip form Package form - QFP 80L
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9.3. PAD Locations
PAD No. PAD Name X Y PAD No. PAD Name X Y
1 2 3 4 5 6 7 8 9
SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 VSS OSC1 OSC2 V1 V2 V3 V4 V5 CL1 CL2 VDD M D RS RW E DB0 DB1
1410 1270 1137 1017 897 777 657 537 417 297 177 57 -63 -183 -303 -423 -543 -663 -783 -903 -1023 -1143 -1271 -1411 -1391 -1391 -1391 -1391 -1391 -1391 -1391 -1391 -1391 -1391 -1391 -1391 -1391 -1391 -1391 -1391
1164 1164 1164 1164 1164 1164 1164 1164 1164 1164 1164 1164 1164 1164 1164 1164 1164 1164 1164 1164 1164 1164 1164 1164 932 784 624 504 384 264 144 24 -96 -216 -336 -456 -576 -696 -816 -955
41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
DB2 DB3 DB4 DB5 DB6 DB7 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23
-1410 -1272 -1140 -1013 -890 -770 -637 -517 -397 -277 -157 -37 83 203 323 443 563 683 803 923 1043 1163 1283 1410 1390 1390 1390 1390 1390 1390 1390 1390 1390 1390 1390 1390 1390 1390 1390 1390
-1165 -1165 -1165 -1165 -1165 -1165 -1165 -1165 -1165 -1165 -1165 -1165 -1165 -1165 -1165 -1165 -1165 -1165 -1165 -1165 -1165 -1165 -1165 -1165 -963 -802 -662 -532 -412 -292 -172 -52 68 188 308 428 548 683 818 963
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11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
10
(c) Sunplus Technology Co., Ltd. Proprietary & Confidential
43
OCT. 03, 2001 Version: 1.0
SPLC780C
9.4. Package Configuration
QFP 80L Top View
80 SEG23 79 SEG24 78 SEG25 77 SEG26 76 SEG27 75 SEG28 74 SEG29 73 SEG30 72 SEG31 71 SEG32 70 SEG33 69 SEG34 68 SEG35 67 SEG36 66 SEG37 65 SEG38
SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG09 SEG08 SEG07 SEG06 SEG05 SEG04 SEG03 SEG02 SEG01 VSS OSC1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
64 63
SEG39 SEG40
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62 COM16 61 COM15 60 COM14 59 COM13 58 COM12 57 COM11 56 COM10 55 54 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 DB7 DB6 DB5 DB4 DB3 DB2
SPLC780C-XX
53 52 51 50 49 48 47 46 45 44 43 42 41
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39 DB0
OSC2
VDD
(c) Sunplus Technology Co., Ltd. Proprietary & Confidential
44
DB1
CL1
CL2
RW
RS
V1
V2
V3
V4
V5
M
D
E
40
OCT. 03, 2001 Version: 1.0
SPLC780C
9.5. Package Information
QFP 80L Outline Dimensions
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(c) Sunplus Technology Co., Ltd. Proprietary & Confidential
45
OCT. 03, 2001 Version: 1.0
SPLC780C
10. DISCLAIMER
The information appearing in this publication is believed to be accurate. Integrated circuits sold by Sunplus Technology are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. SUNPLUS makes no warranty, express, statutory implied or by description regarding the information in this publication or FURTHER, SUNPLUS MAKES NO WARRANTY OF SUNPLUS reserves the right to halt production or alter the specifications and regarding the freedom of the described chip(s) from patent infringement. MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. prices at any time without notice. publication are current before placing orders.
Accordingly, the reader is cautioned to verify that the data sheets and other information in this Products described herein are intended for use in normal commercial applications.
Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support equipment, are specifically not recommended without additional processing by SUNPLUS for such applications. Please note that application circuits illustrated in this document are for reference purposes only.
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(c) Sunplus Technology Co., Ltd. Proprietary & Confidential
46
OCT. 03, 2001 Version: 1.0
SPLC780C
11. REVISION HISTORY
Date Revision # Description Page
JUN. 04, 2001 OCT. 02, 2001
0.1 1.0
Original 1. Delete "PRELIMINARY" 2. Correct "8.3 SPLC780C-03" 3. Add "8.4 SPLC780C-08" and "8.12 SPLC780C-19" 32 33, 41
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(c) Sunplus Technology Co., Ltd. Proprietary & Confidential
47
OCT. 03, 2001 Version: 1.0


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